Logic circuits can be classified into two broad categories, combinational logic circuits and sequential logic circuits. The basic building block of sequential logic circuits is the flip-flop, also called a bi-stable multi-vibrator or latch. In most cases, logic circuits employ both sequential and combinational logic.
FIG. 1 (prior art) depicts an exemplary logic circuit 100 that includes both combinational and sequential logic elements. Logic circuit 100 is a divide-by-five counter with a NAND gate 105 and a NOR gate 106 in a feedback path of a series of differential-input flip-flops 110. Logic circuit 100 receives a pair of complementary clock signals C and Cb, which extend to clock input terminals of each of the flip-flops 110. Circuit 100 produces a pair of complementary clock signals C/5 and Cb/5 with a frequency one fifth that of the input clock signals. The differential nature of circuit 100 allows for higher clock frequencies than would a similar divide-by-five circuit using single-ended sequential logic elements.
FIG. 2 (prior art) depicts an embodiment of a differential-input flip-flop 110 for use in circuit 100 of FIG. 1. The operation of flip-flop 110 is commonly understood by those of skill in the art, so a detailed description of flip-flop 110 is omitted here for brevity.
If manufactured using commonly available CMOS processes, flip-flop 110 can perform with clock frequencies as high as about 2 GHz. Unfortunately, modern high-speed digital communication systems employ clock and data recovery circuits operating in the 10 Gb/s range. The frequency response of flip-flop 110 is therefore insufficient to meet the needs of some modern systems.
Differential return-to-zero-type flip-flops have been developed for high-frequency operation, but some embodiments do not work well at lower frequencies (below about 1 GHz), particularly when the manufacturing process or operating environment (e.g. temperature) changes. Therefore, a high-speed differential flip-flop that overcomes these disadvantages is desirable.